1. Field of the Invention
The present invention generally relates to a semiconductor device, and more particularly to a semiconductor substrate, a semiconductor device having a ferroelectric film and method for fabricating the semiconductor device.
2. Description of the Related Art
A semiconductor memory device such as DRAM and SRAM is widely used as a high speed main memory device in an information processing devices such as a computer. However, since this memory device is a volatile memory device, the information stored therein will be lost once the power is turned off. Meanwhile, a non-volatile magnetic disk device is used as a large size auxiliary memory device for storing programs and data.
The magnetic disk device has problems such as, having a large size, being mechanically vulnerable, consuming a large amount of electricity, and having a slow access speed when reading/writing information. In recent years, as another non-volatile auxiliary memory device, an EEPROM or a flash memory, which stores information by applying voltage to a floating gate electrode, is widely used. The flash memory is particularly expected to be used as a large capacity memory device matching to the magnetic disk device since the flash memory has a similar cell structure that allows formation with high integrated density.
However, since information is written by applying hot electron to a floating gate electrode via a tunnel insulating film, the EEPROM or flash memory has problems such as requiring time for writing information and deteriorating the tunnel insulating film from repetitive writing/erasing of information. Such deteriorated tunnel insulating film causes writing and erasing operation to become unsteady.
As another memory device, a ferroelectric memory device (hereinafter referred to as “FeRAM”), which stores information by intrinsic polarization of a ferroelectric film, is proposed. Similar to the DRAM, the FeRAM has each memory cell transistor of the FeRam structured as a single MOSFET, in which the dielectrics in the memory cell capacitor is replaced with ferroelectric material such as PZT (Pb (Zr, Ti) O3), PLZT (Pb (Zr, Ti, La)O3), SBT (SrBi2Ta2O3), or SBTN (SrBi2 (Ta, Nb) 2O3). Thus structured, integration of high integrated density can be obtained. Since the FeRAM controls intrinsic polarization of a ferroelectric capacitor by impressing of electric field, writing speed is no less than 1000 times faster than that of the EEPROM or the flash memory which write information by applying hot electron, and also reduces electric power consumption to approximately 1/10. In addition, since the FeRAM requires no tunnel oxide film, the FeRAM can attain a longer longevity, and perform re-writing operations one hundred thousand times more than the flash memory.
FIG. 1 shows a conventional FeRAM 20.
In FIG. 1, the FeRAM 20 is formed on a P-type or N-type Si substrate 21, in which the Si substrate 21 is defined by a field insulating film 22 and includes a P-type well 21A and an N-type well 21B. A gate electrode 24A, having a polycide structure, is formed above the P-type well 21A via a gate insulating film 23A. Further, a gate electrode 24B, also having a polycide structure, is formed above the N-type well 21B via a gate insulating film 23B. In the P-type well 21A, N-type diffusion areas 21a, 21b are formed on both sides of the gate electrode 24A. In the N-type well 21B, P-type diffusion areas 21c, 21d are formed on both sides of the gate electrode 24B. Outside the active area, the gate electrode 24A extends over a field oxide film (element separation film) 22, and forms a part of an FeRAm word line (WL).
Each of the gate electrodes 24A, 24B has a side wall insulating film. Above the Si substrate 21, an SiON cover film 25 is formed in a manner covering the field insulating film 22, in which the SiON cover film 25 is formed into a thickness of approximately 200 nm by a CVD method.
A SiO2 layer-interposed insulating film 26 is formed in a manner covering the cover film 25, in which the SiO2 layer-interposed insulating film 26 is formed into a thickness of approximately 1 μm by a CVD method employing TEOS gas. The surface of the layer-interposed insulating film 26 planarized by a CMP method.
A ferroelectric capacitor is formed above the planarized layer-interposed insulating film 26, in which the ferroelectric capacitor has a lower electrode 27, a ferroelectric capacitor insulating film 28, and an upper electrode 29 orderly stacked above each other. The lower electrode 27 is formed of a Ti film with a thickness of 10–30 nm (more preferably, approximately 20 nm) and a Pt film with a thickness of 100–300 nm (more preferably, approximately 175 nm). The ferroelectric capacitor insulating film 28 is a film of PZT ((Pb (Zr, Ti) O3) or PZLT ((Pb, La) (Zr, Ti)O3) with a thickness of 100–300 nm (more preferably, approximately 240 nm). The upper electrode 29, disposed above the ferroelectric capacitor insulating film 28, is a film of IrOx with a thickness of 100–300 nm (more preferably, 200 nm). Further, the Ti film and the Pt film are formed, typically, by sputtering. The ferroelectric capacitor insulating film 28, typically after sputtering, is crystallized by rapid thermal processing in a oxygen atmosphere of 725° C. for 20 seconds. It is preferable to add Ca and Sr to the ferroelectric capacitor insulating film 28. Further, the ferroelectric capacitor insulating film 28 can not only be formed by a sputtering method, but alternatively formed by a spin-on method, a sol-gel method, a MOD (metal organic deposition) method, or a MOCVD method. As alternatives for using a PZT film or a PLZT film as the ferroelectric capacitor insulating film 28, an SBT (SrBi2 (Ta, Nb)2 O9) film, or a BTO (Bi4Ti2O12) film may, for example, be used. Furthermore, by using a high dielectric film (e.g. a BST ((Ba, Sr)TiO3) film, or a STO (SrTiO3) film) as an alternative for the ferroelectric capacitor insulating film 28, a DRAM can be formed. Further, the IrOx film of the upper electrode 29 is typically formed by sputtering. A Pt film or an SRO (SrRuO3) film may be used as alternatives for the IrOx film.
In a case where the ferroelectric capacitor is exposed to a reducing atmosphere, particularly to hydrogen, during a semiconductor process, the ferroelectric capacitor insulating film 28 is easily deoxidized, thereby resulting to severe deterioration of electric property. Therefore, the ferroelectric capacitor insulating film 28 is covered by an encapsulation layer 330A formed of Al2O3, in which the encapsulation layer 330A is formed with a thickness of approximately 50 nm by employing a sputtering method. Further, the encapsulation layer 330A is covered by another encapsulation layer 330 also formed of Al2O3, in which the other encapsulation layer 330 is formed with a thickness of approximately 20 nm. The other encapsulation layer 330 serves as a barrier layer for preventing hydrogen from entering.
An SiO2 layer-interposed insulating film 30 is formed on the encapsulation layer 330 by a CVD method (more preferably, a Plasma CVD (P-CVD) method) using, for example, SiH4, a polysilane compound such as Si2F6, Si3F8, Si2F3Cl, SiF4, or TEOS, in which the SiO2 layer-interposed insulating film 30 is formed above the upper electrode 29 with a thickness of approximately 400 nm. Contact holes 30A, 30B are formed in the layer-interposed insulating film 30 for exposing the upper and lower electrodes 29, 27, respectively. Further, contact holes 30C, 30D, 30E, and 30F are disposed in the layer-interposed insulating film 26 for exposing the diffusion areas 21a, 21b, 21c, and 21d, respectively. A contact hole 30G is formed in the layer-interposed insulating film 30 for exposing the word line patter WL formed on the element separation film 22.
In the conventional FeRAM 20 shown in FIG. 1, contacting films 31A and 31B, formed of conductive nitride material (e.g. TiN) with a thickness of approximately 50 nm, are respectively formed in the contact holes 30A and 30B in a manner directly contacting the inner wall surfaces of the contact holes 30A and 30B, or directly contacting the surfaces of the exposed upper or lower electrodes 29, 27. By applying a CVD method using a mixed gas of WF6, Ar, and H2, a conductive plug (W plug) 32A, formed of W, is formed on the contacting film 31A of the contact hole 30A, and a conductive plug (W plug) 32B, also formed of W, is formed on the contacting film 31B of the contact hole 30B.
In a likewise manner, contacting films 31C–31G are formed at the inner wall surfaces of the contact holes 30C–30G, and W plugs 32C–32G are formed on the contacting films 31C–31G.
Further, wiring patterns 33A–33F, formed of A1, are disposed on the layer-interposed insulating film 30 in correspondence with the W plugs 32A–32G. The wiring patterns 33A–33F are covered by a further layer-interposed insulating film 34 formed of SiO2, in which the layer-interposed insulating film 34 is formed by a P-CVD method using, for example, SiH4, a polysilane compound such as Si2F6, Si3F8, Si2F3Cl, SiF4, or TEOS, similar as the layer-interposed insulating film 30.
Further, a protective film 35, formed of SiO2, is formed on the layer-interposed insulating film 34 with a thickness of 100 nm or more by using a P-CVD method. The protective film 35 serves to cover exposed slits (cavities) formed after a planarizing process (CMP) executed after the formation of the layer-interposed insulating film 34.
Further, contact holes 35A, 35B are formed in a manner piercing the protective film 35 and the layer-interposed insulating film 34 for exposing the wiring patterns 33A and 33F, respectively. Further, W plugs 37A, 37B are formed on the inners wall surface of the contact holes 35A, 35B via contacting films (TiN contacting layers) 36A, 36B.
Further, wiring patterns 38A, 38B, formed of A1 or A1 alloy, are formed on the protective film 35 in a manner contacting the W plugs 37A, 37B. In forming the wiring patterns 38A, 38B, the contacting films 36A, 36B are disposed extending between the wiring patterns 38A, 38B and the protective film 35 in a manner covering the inner wall surfaces of the contact holes 35A, 35B.
Further, a layer-interposed insulating film 39, formed in a manner similar to that of layer-interposed insulating film 30 and 34, is disposed covering the wiring patterns 38A, 38B. Further, a protective film 40, similar to the protective film 35, is formed on the layer-interposed insulating film 39. Then, wiring patterns 41A–41E including a bit line (BL) pattern is formed on the protective film 40.
The FeRAM 20 shown in FIG. 1 is fabricated according to the steps shown in FIGS. 2A–2F.
In the step shown in FIG. 2A, the Si substrate 21 is provided with diffusion areas 21a–21d and is mounted with polycide gate electrodes 24a, 24B. The SiO2 layer-interposed insulating film 26 is formed with a thickness of approximately 1 μm on the Si substrate 21 in a manner covering the polycide gate electrodes 24A, 24B by using the P-CVD method with TEOS. Further, the SiO2 layer-interposed insulating film 26 is planarized with the CMP method. Then, on the planarized layer-interposed insulating film 26, the Ti film and the Pt film are orderly deposited with a thickness of 20 nm and 175 nm, respectively. Then, on the deposited film, the PLZT film (preferably added with Ca and Sr) is formed with a thickness of 240 nm by sputtering. Thereby, the ferroelectric film is obtained. The PLZT film (ferroelectric film) is crystallized by being subjected to rapid thermal processing in an oxygen atmosphere of 725° C. for 20 seconds at a heating rate of 125° C./second. After the ferroelectric film is crystallized, the IrOx film with a thickness of 200 nm is formed on the ferroelectric film by the sputtering method.
Then, the upper electrode 29 is formed by patterning the IrOx film with resist (resist process). After the resist process, the ferroelectric film is thermally processed again in an oxygen atmosphere of 650° C. for 60 minutes, to thereby compensate for the deficit of oxygen in the ferroelectric film during the processes of sputtering and patterning the IrOx film.
Then, a resist pattern is formed in a manner covering the upper electrodes. Using the resist pattern as a mask, the ferroelectric film is patterned, to thereby obtain the ferroelectric capacitor insulating film 28. After the ferroelectric capacitor insulating film 28 is formed, the ferroelectric film is thermally processed in a nitrogen atmosphere, so as to dehydrate the inside of the layer-interposed insulating film 26.
Further, the Al2O3 film is sputtered to the Pt/Ti layer in normal temperature in a manner covering the ferroelectric capacitor insulating film 28 and the upper electrode 29. Thereby, the encapsulation layer 330A is obtained for protecting the ferroelectric capacitor insulating film 28 from H2. After the encapsulation layer 330A is formed, a thermal process is executed in an oxygen atmosphere of 550° C. for 60 minutes so that the film quality of the encapsulation layer 330A can be enhanced.
Then, a resist pattern is formed on the encapsulation layer 330A. Using the resist pattern on the encapsulation layer 330A as a mask, the Pt/Ti layer is patterned, to thereby obtain the lower electrode 27.
Further, after the resist used for obtaining the lower electrode 27 is removed, and executing a thermal process of 350° C. for 30 minutes, the Al2O3 film is sputtered on the layer-interposed insulating film 26. Thereby, another encapsulation layer 330 (second encapsulation layer) is formed in a manner covering the encapsulation layer 330A.
Further, a thermal process of 650° C. is executed for 30 minutes after the formation of the encapsulation layer 330 so that the damage created in the ferroelectric capacitor insulating film 28 can be relieved. Further, the layer-interposed insulating film 30, having a thickness of approximately 1200 nm, is formed on the encapsulation layer 330 by a P-CVD method using, for example, SiH4, a polysilane compound such as Si2F6, Si3F8, Si2F3Cl, SiF4. Alternatively, the layer-interposed insulating film 30 may also be formed by using TEOS. A thermal excitation CVD method or a laser excitation CVD method may be employed as alternatives of the P-CVD method. Then, the layer-interposed insulating film 30 is polished and planarized by the CMP method until having a thickness of approximately 400 nm (measured from the surface of the upper electrode 29).
Next, in the step shown in FIG. 2B, the layer-interposed insulating film 30 is dehydrated by using N2 plasma or N2O plasma. Then, in a resist process using CHF3 and a mixed gas of CF4 and Ar, the contact holes 30A and 30B are formed in the layer-interposed insulating film 30 in a manner penetrating the encapsulation layers 330 and 330A and allowing the upper electrode 29 and the lower electrode 27 to be exposed. Then, in this state, a thermal process is executed in an oxygen atmosphere at 60° C. for 60 minutes. This enables recovery in film quality of the ferroelectric capacitor insulating film 28 deteriorated during the formation of the contact holes 30A and 30B.
In the step shown in FIG. 2C, resist pattern R having aperture portions corresponding to contact holes 30C–30F is applied to the structure shown in FIG. 2B. Using the resist pattern R as a mask, the layer-interposed insulating films 30 and 26 are patterned to form the contact holes 30C–30F, thereby exposing the diffusion areas 21a–21d. Since the formation of contact hole G (see FIG. 1) is simple, a detail description thereof is omitted.
In the step shown in FIG. 2D, the resist pattern R is removed, and a pre-treating process of Ar plasma etching is executed. Then, the TiN film 31 is sputtered to the layer-interposed insulating film 30 in a manner continuingly covering the inner wall surface and bottom surface of the contact hole 31A and the inner wall surface and bottom surface of the contact hole 31B. The TiN film is formed with a thickness of approximately 50 nm. The TiN film contacts the exposed part of the upper electrode 29 at the bottom surface of the contact hole 30A, and contacts the exposed part of the lower electrode 27 at the bottom surface of the contact hole 30B. Further, the TiN film also contacts the exposed parts of the diffusion areas 21a–21d at the contact holes 30C–30F.
In the step shown in FIG. 2E, the W layer 32 is deposited on the TiN film 31 by a CVD method using WF6, Ar, and H2 in a manner filling the contact holes 30C–30F.
Although H2 is used in the CVD method in the step shown in FIG. 2E, the H2 will not reach the ferroelectric film 28 since the ferroelectric capacitor containing the ferroelectric film 28 is overlappingly covered by the encapsulation layers 330, 330A and the TiN film 31. Therefore, the property of the ferroelectric capacitor can be prevented from being deteriorated by deoxidization.
In the step shown in FIG. 2F, the W layer 32 on the layer-interposed insulating film 30 is polished/removed by a CMP method. As a result, W plugs 32A–32F, formed from the portions of the W layer remaining in the contact holes 30A–30F, are obtained. In addition, as a result of the use of the CMP method, the TiN film on the layer-interposed insulating film 30 is planarized, to thereby obtain TiN patterns 31A–31F corresponding to the contact holes 30A–30F.
Among the W plugs 32A–32F, although the W plug 32A, formed of IrOx, contacts the upper electrode 29 via the TiN pattern 31A, the TiN pattern 31A does not react to conductive oxides such as IrOx. Therefore, no increase of contact resistance will occur.
Then, by performing a typical procedure of forming a multi-layer wiring structure to the structure shown in FIG. 2F, the FeRAM shown in FIG. 1 is obtained.
With the above-described conventional FeRAM 20 using the Al2O3 encapsulation layers 330, 330A as hydrogen barriers, the thickness of the encapsulation layers 330, 330A are required to be increased for effectively preventing entry of hydrogen and maintaining the electric property of the ferroelectric capacitor in a case where the size of the ferroelectric capacitor is reduced in correspondence with size-reduction of the FeRAM 20. Accordingly, in recent FeRAMs, the Al2O3 encapsulation layer 330A is provided with an increased thickness of, for example, 50 nm, and the Al2O3 encapsulation layer 330 is provided with an increased thickness of, for example, 100 nm.
However, in using the FeRAM 20 having encapsulation layers 330, 330A with increased thicknesses, corrosion or peeling may occur at an alignment mark situated at a scribe line. Furthermore, alignment becomes difficult, particularly, during the formation of the contact holes 30A, 30B in the step shown in FIG. 2B, and particles are created, thereby resulting to a considerable yield loss in fabricating the FeRAM.